Advancement in chip technology has resulted in the development of embedded processors and controllers. Embedded processors and/or controllers may include microprocessor and/or microcontroller circuitry that has been integrated into single package containing associated companion logic and peripherals. Embedded processors differ from microprocessors and microcontrollers in that microprocessors and microcontrollers are typically coupled with associated logic on a circuit board to implement a specified application.
Further advancements in chip technology have increased packaging density to the point where it is now possible implement a standalone application on a single chip. In this regard, the resulting integrated circuit (IC) is called a system on a chip (SoC). A SoC may include one or more microprocessor and/or microcontroller elements, peripherals, associated logic and memory all fabricated on a densely packaged IC. For example, a SoC for a broadband set-top box may include a receiver, a transmitter, a digital signal processor, one or more encoders and decoders, random access memory (RAM), and non-volatile memory (NVM), all of which may be integrated on a single chip. The peripherals are typically called embedded peripherals. In the case of a memory element, the memory element may be called an embedded memory.
Due to the ubiquitous use of integrated circuits in electronic devices and systems, testing of such integrated circuits in the fabrication process must be accomplished to ensure an effective production yield. In particular, testing is of importance in integrated circuits (ICs) that incorporate embedded memories. Embedded memories may be tested using a built-in self test (BIST) controller, for example, that supplies a series of pre-determined test patterns to one or more embedded memories.
The built-in self test controller is implemented using a number of gates and is incorporated into an integrated circuit (IC) during manufacturing. The built-in self test controller operates by supplying a number of input test patterns to components within the integrated circuit which are referred to as the device under test (DUT). The device under test may generate an output signal which corresponds to the input test pattern. In order to evaluate the performance of the integrated circuit, the output signal generated by the device under test may subsequently be compared against a set of expected test signal responses corresponding to the input test pattern.
A built-in self test controller utilizes selected built-in test patterns that cover a majority of the possible memory failure scenarios. Accordingly, the BIST test patterns for an integrated circuit are manufactured into or permanently burned into the chip prior to commercial usage. Accordingly, if there are any design changes in hardware and/or firmware, new test patterns cannot be readily implemented. Furthermore, the BIST circuitry and logic may utilize expensive chip real estate.
The packing density of an integrated circuit may further affect the testing of embedded memories, for example, read-only memory (ROM) and random access memory (RAM) such as dynamic RAM (DRAM), static RAM (SRAM), and dual-data rate RAM (DDR). In the case of integrated circuits that contain a small number of embedded memories and are therefore less densely packed, the use of built-in self test technology may not be advantageous. In this regard, the implementation of a built-in self test controller circuitry within each integrated circuit may not be desirable since the overall cost to implement testing increases with each unit of product manufactured.
Although built-in self test technology provides a significant role in a component level test where access to the embedded virtual component is difficult or impossible, there exists associated drawbacks or disadvantages that may result in designers utilizing alternative approaches to testing embedded devices such as embedded memory. For example, a significant amount of additional circuitry or logic is generally required to implement the built-in self test controller. Also, the number of gates used to realize a built-in self test controller may be in the tens of thousands. As a consequence, in certain instances, it may be beneficial to rely on secondary modes of testing.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.